Incremental Data Converters for Sensor Interfaces describes the motivation for using incremental analog-to-digital converters (IADCs), including the theoretical foundations of their operation, the trade-offs in their use, and the practical issues in the circuit analysis and design of IADCs. The text covers core foundational knowledge such as the key algorithms used, circuits for single-stage and multi-stage IADCs, the design of the digital post filters for single- and multi-stage IADCs, IADC applications in measurement and instrumentation, medicine, imagers, and IoT, and comparison of delta-sigma (D-S) and incremental ADCs (IADCs) in terms of accuracy, latency, and multiplexed operation.
To aid in reader comprehension and serve as an excellent classroom learning resource, Incremental Data Converters for Sensor Interfaces includes in-text problems and homework for graduate studies, along with helpful computer codes in MATLAB and Simulink.
Additional topics covered in Incremental Data Converters for Sensor Interfaces include: - Sensors and sensor interfaces, mixed-mode (analog-digital) communication and consumer signal chains, and ADC algorithms - Quantization errors vs. quantization noise, and performance parameters and figures of merit, including resolution, linearity, accuracy, bandwidth, latency, and power dissipation - Nyquist-rate and oversampling data converters, noise-shaping ADCs, and basic architectures for IADCs, including single- and multi-stage designs and discrete vs. continuous-time operation - Loop filter design, D/A converter design, dynamic element matching and digital calibration, and quantizer design
With comprehensive coverage of foundational knowledge surrounding the subject, various real-world examples, and helpful learning aids, Incremental Data Converters for Sensor Interfaces is an essential resource for graduate students in electronics programs, along with industrial circuit design professionals.
Table of Contents
About the Authors ix
Preface xi
Abstract & Keywords xiii
1 Fundamentals of Analog-to-Digital Data Converters (ADCs) 1
1.1 Performance Parameters for Analog-to-Digital Converters 1
1.2 Algorithms and Architectures for Analog-to-Digital Converters 4
1.2.1 Dual-Slope (Integrating) ADCs 5
1.2.2 Delta-Sigma A/D Converters 6
1.2.3 Successive Approximation A/D Converters 11
1.2.4 Flash A/D Converter 13
1.2.5 Incremental A/D Converter 14
References 15
2 Delta-Sigma ADCs 17
2.1 Sampled-DataΔΣ ADCs 18
2.2 Loop Filter Structures and Circuits for Sampled-Data ΔΣ ADCs 20
2.3 Optimization of Zeros and Poles for Sampled-Data ΔΣ ADCs 22
2.4 Limitations on the Performance of Sampled-Data ΔΣ ADCs 23
2.5 Multistage Sampled-Data ΔΣ ADCs 26
2.6 Continuous-Time ΔΣ ADCs 27
2.7 Advantages and Limitations of Continuous-Time ΔΣ ADCs 31
References 36
3 Single-Stage Incremental Analog-to-Digital Converters 39
3.1 The First-Order IADC 39
3.2 Higher-Order Single-Stage IADCs 42
3.2.1 Analysis and Design of a Second-Order IADC 42
3.2.2 The Design of Higher-Order IADCs 44
3.2.3 IADC Circuit Techniques 46
3.2.4 Comparison of IADCs and ΔΣ ADCs 47
3.3 Decimation Filter and the Overall Design of IADCs 48
3.3.1 Cascade-of-Integrators (CoI) 48
3.3.2 Thermal Noise 48
3.3.3 Optimized Digital Filter Design for a Single-Stage IADC 49
3.3.4 Multiple-Stage IADCs and Extended Counting ADCs 52
3.4 Estimation of Power Consumption 53
3.4.1 Power Consumption for Small Signal Settling 53
3.4.2 Power Consumption for Slewing 55
3.4.3 An Example 56
References 57
4 Multistage and Extended Counting Incremental Analog-to-Digital Converters 59
4.1 Multistage Noise Shaping (MASH) Incremental ADCs 59
4.1.1 The Design of MASH IADCs 59
4.1.2 Trade-Offs in the Design of MASH IADCs 61
4.1.3 Hybrid Schemes for an IADC and a Nyquist-Rate ADC 62
4.1.4 Extended Counting with Hardware Sharing 64
4.2 Design Examples 66
4.2.1 IADC with Two-Capacitor Counting 66
4.2.2 Switched-Capacitor Implementation of the Example IADC 69
4.2.3 Nonideal Effects 72
4.2.4 Measured Performance 73
4.3 The Zoom Incremental ADC 77
4.3.1 Two-Stage 0-L IADCs 77
4.4 Zoom ADC Design Example 79
4.4.1 Nonideal Effects 80
4.4.2 Measured Performance 81
References 83
5 Design Examples 87
5.1 A Third-Order 22-Bit IADC 87
5.2 A 16-Bit Multistep IADC with Single-Opamp Multi-Slope Extended Counting 92
5.3 Multistep IADCs 100
5.3.1 Two-Step IADCs 100
5.3.2 Switched-Capacitor Circuitry 104
5.3.3 Measured Performance 107
5.3.4 A Two-Step Third-Order IADC 108
5.3.5 Conclusion 110
5.4 A Hybrid Continuous-Time Incremental and SAR Two-Step ADC with 90.5 dB Dynamic Range Over 1 MHz Bandwidth 111
5.5 A Multistage Multistep IADC 118
5.5.1 Design of a MASH 2-1 IADC 118
5.5.2 An IADC2-1 Versus a MASH 2-1 ΔΣ ADC 120
5.5.3 Noise Consideration for Higher-Order IADCs 121
5.5.4 The Proposed Multistage Multistep IADC 122
5.5.5 Circuit Implementation 127
5.5.6 Measured Performance 132
5.5.7 Conclusion 137
References 137
Index 143
